How to create a simple serial UART Transmitter in verilog HDL

Most Universal Asynchronous Receiver Transmitter (UART) that I found online, are too complicated and difficult to understand, here I will explain some simple theory and also code on how to build one.

First lets talk about how transmitters work. The basic principle is to send multiple bits of data over a single line. In our transmitter, this data is parallel, however to reduce the number of wires required, we use serial communication that is converted to parallel at the receiving end.

The basic things that we need are the following:

1. A clock divider ( our counter)

This is enables us to send data at a certain speed (baud rate). Our receiver will sample and take the data bit by bit.

1. A shift register

We need to know how many bits at a time we are transmitting, our shift register will have a start bit, data bits, parity bit(optional), end bit.

1. A state diagram

Before writting any code, we must think of what we need to create and the best way is creating a state diagram of our design. We know for a transmitter we need 2 states, IDLE and TRANSMITTING.

After having a state diagram, now we can calculate what our counter will be. This is done by using:

counter = FPGA clock speed/ baud rate

In this example I use a baud rate of 9600, making my counter = 5208.

Last, we calculate our shift register and finish writing our state machine. In my sample code I use a start bit, parity bit, 8 bits of data and end bit. This is 11 bits total.

Both images in step 2 and 3 together in the same module complete our transmitter code required to program to the FPGA. This code will work with another FPGA connected serially or with windows hyperterminal among other hardware. Can be easily modifiable to work with much more.

Last, we create a test fixture to fix any errors and simulate our program before programming the FPGA.

This concludes the Transmitter. Please leave comments if you have any questions or feel there is something missing here.